1. Field of the Invention
The present invention relates to a construction and fabrication method of a semiconductor integrated circuit device used as a current regulating diode (Hereinafter referred to as a CRD) and more particularly to a construction and fabrication method for realizing suitable electrical characteristics as a current regulating diode of a depletion type (surface inversion type, normally-on type) N channel MOS (NMOS) transistor in which a gate, source and substrate are electrically connected (cabled).
2. Discussion of Related Art
FIG. 58 is an explanatory diagram for showing an electrical function of a prior art CRD for which a junction field effect transistor (hereinafter referred to as a JFET) is generally used. The JFET comprises a drain 18002, gate 18001 and source 18003, and the gate electrode 18001 is connected with the source electrode 18003.
FIG. 59 is an explanatory diagram for showing an electrical function of a CRD. An anode 18004 and cathode 18005 are included and arrow 18009 indicates a direction of current which becomes a regulated current.
FIG. 60 is an outside view of the prior art CRD. A CRD chip 18008 is built in a cylindrical glass mold 18007 type outer case (package) having a length of several mm and diameter of about 1 mm and a lead wire for electrode 18006 (referred to as an axial lead) is provided in both directions respectively as an anode electrode and cathode electrode.
Having the construction as described above, the prior art CRD has the following problems.
FIG. 61 is a graph showing a current-voltage characteristic of the prior art JFET CRD. As seen from the graph, the lowest voltage VL for obtaining a desired regulated current value is a voltage value of more than 5 V. The VL rises up to 7 V or 10 V depending on the current value. This is because the JFET is used and the pinch off voltage of the channel is high. Such high voltage cannot be used for circuits having a power voltage of 5 V, 3 V or 1.5 V which are standards of current electronic circuits. Contrary to that, because it is a JFET and allows one to considerably raise a breakdown voltage VB to about 100 V, an operating maximum voltage VH may be easily set at 24 V or 26 V. However, because the JFET CRD basically operates as a bipolar element (minority carrier element), a time response on the OFF side (accumulation of minority carriers) in response to a fluctuation of voltage is very slow and hence it conventionally causes many noises.
Further, concerning a matter of production, while it is fabricated targeting for a certain value (rating) of IP (a rating of a current regulating diode as a product is a value when it is supplied by compensating like 10 mA.+-.10% for example. IP denotes a value of regulated current at a standard voltage value VP and VL denotes the lowest voltage which falls within its .+-.range), there is a problem that IP of the finished product actually fluctuates by about .+-.20%. Accordingly, because they are selectively shipped or a variation of products having different current values are created in the fabrication and are lined up in reality, their yield (ratio of good products) is bad, their stock increases and their production cost becomes very high.
On the other hand, a CRD made from a depletion type N channel MOS transistor in which a gate, source and electrode are electrically connected undergoes more fluctuation in the fabrication. The fluctuation exceeds .+-.30% and it increases further when VH is increased. This is because the fluctuation of the depletion state (threshold voltage: VTH) of the channel increases by all means in the fabrication.
Further, while VL can be set low, VH can be set at 7 V or 10 V at most. Although the standard power voltage of electronic circuits has come to be less than 5 V, a 12 V system or 24 V system is still used as a standard for a driving system requiring a higher power and a CRD for such use requires about 24 V of maximum voltage VH. Here, a thickness of gate insulating film (gate TOX) has to be increased in order to increase VH. Then a disadvantage that VTH fluctuates further is brought about. The greater the thickness of the gate insulating film, the greater the fluctuation becomes. In addition to that, when the gate insulating film thickness is increased, a trans-conductance (gm) of the MOS transistor drops and a channel width or so-called W width for obtaining a necessary drain current ID, i.e., IP, has to be widened, hence increasing the chip size. Thus the prior art CRD has disadvantages that its yield is bad, chip size is large and its production cost is high.